Mitronics Book Abstract
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Published: March 30, 2007
DEVELOPMENTS
IN THE FIELD OF FPGA:
The development of
mitrionics and the formation of the mitrion platform lead to various advancements
in FPGA technology in recent years, both at a device level and in the wider
ecosystem. The advent of multi-million gate devices, embedded microprocessors,
dedicated signal-processing units and high-speed serial links has made FPGAs
increasingly competitive in both high and low-end embedded applications.
Critically, these features have helped invoke a realization that FPGAs can
perform floating point arithmetic – the latest Virtex-4 family from Xilinx
offers a peak performance of 100GFLOPs.
FPGA
organization
Significantly for the Defense
industry, there is now a wide selection of COTS vendors offering FPGA
technologies on hardware platforms across a variety of forms and architectures,
ranging from the FPGA-centric to the co processing approach. The last 2 years
has also seen a marked change in the FPGA community with initiatives such as
Open FPGA demonstrating the type of collaborative approach that will deliver
longevity to the COTS FPGA market and ultimately deliver the benefits of choice
to the end users.
At a device level the Cell
Processor, released by IBM in 2005, offers the type of processing performance
that, much like FPGAs, makes for a compelling proposition. With a peak
performance of 200GFLOPs it has huge potential for the type of real-time data
intensive applications so common to the military. But achieving formal
acceptance in the Defense world is a long-term play, as the
FPGA community knows only too
well. With acceptance of the Cell processor in mind, the single biggest concern
for military users is likely to be the fact that only one COTS vendor
currently offers Cell-based platforms.
The Mitrion Virtual Processor:
The key to making it possible to
run software in FPGAs is to put a processor in the FPGA. This allows the user
to program the processor instead of designing an electronic circuit to place in
the FPGA. To get high performance in an FPGA, the processor is adapted for the
program to make efficient use of the resources available on the FPGA. The
result is a configuration file for the FPGA, which will turn it into a
co-processor running your software algorithm. This approach allows the software
developer to focus on writing the application instead of getting involved in
circuit design. The circuit design process has already been done in designing
the Mitrion Virtual Processor.
A Novel Processor Architecture:
The clock speed of a circuit
running in an FPGA will be approximately one order of magnitude lower compared
to fixed silicon (such as a CPU) at the same semiconductor manufacturing
process technology node (currently 90nm), and each gate will use approximately
two orders of magnitude more space. So, an FPGA will be about three orders of
magnitude less efficient compared to a CPU. However, the FPGA is reconfigurable.
In order for a processor in an FPGA to extract the promised 10x to 100x
performance in relation to traditional CPUs, it must fulfill two requirements:
It must be massively parallel and it must be fully adapted to the program it
will run, thus taking advantage of the reconfigurability of the FPGA.
Unfortunately, this is something the classic von Neumann processor architecture
cannot provide.
The Mitrion Virtual Processor
utilizes a novel processor architecture that resembles a cluster-on-a-chip.
Normal computer clusters consist of a number of compute nodes, often standard
PCs, connected in a fixed network. The basic limitation of such a cluster is
the network latency, ranging from many thousands of clock-cycles up to millions
of clock-cycles, depending on the quality of the network. This means that each
node has to run a large block of code to ensure that it has sufficient work to
do while waiting for a response to a message. Lower latency in the network will
allow each node to do less work in between communications.
In the architecture of the
Mitrion Virtual Processor, the entire cluster is on the same FPGA device. The
network is fully adapted in accordance with the program requirements, creating
an ad-hoc, disjunct network with simple point-to-point connections where
possible, and switched only were so required. This allows the network to have a
guaranteed latency of a single clock cycle. The single clock cycle latency
network is the key feature of the Mitrion Virtual Processor architecture. With
a single cycle latency network, it becomes possible for the nodes to
communicate on every clock cycle. This allows the nodes to run a block of code
consisting of only a single instruction. In a node that will only run one
instruction, it becomes possible to do away with all the instruction scheduling
infrastructure of the node, leaving it with only the arithmetic unit for that
specific instruction. Thus the node can also be fully adapted to the program.
The effect of this full
adaptation of the cluster in accordance with the program is that the problem of
instruction scheduling has been transformed into a problem of data packet
switching. For any dynamic part of the program, the network must dynamically
switch the data to the correct node. But the problem of packet switching, being
a network problem, is inherently parallelizable. This is in contrast to the
inherently sequential problem of instruction scheduling in von Neumann
architecture.
Mitrion-C:
To access all the parallelism
available from (and required by) the Mitrion Virtual Processor, a fully
parallel programming language is needed. It is simply not sufficient to rely on
vector parallel extensions or parallel instructions. The Mitrion-C programming
language is designed to make it easy for programmers to write parallel software
that make the best use of the Mitrion Virtual Processor. Mitrion-C has an
easy-to-learn C-family syntax, but the focus is on describing data dependencies
rather than order of execution. The syntax of Mitrion-C is designed to aid the
programmer in achieving high performance in a parallel machine, just like
ANSI-C is designed to achieve high performance in a sequential machine. Thus
the Mitrion-C compiler is able to extract all the parallelism of the algorithm
being developed. It should be noted, though, that Mitrion-C is purely a
software programming language, there are no elements of hardware design in
Mitrion-C.
The Mitrion Platform:
Together with Mitrion-C and the
Mitrion Virtual Processor, the Mitrion Software Development Kit (SDK) completes
the Mitrion Platform. The Mitrion SDK consists of:
• A Mitrion-C compiler for the Mitrion Virtual
Processor,
• A graphical simulator and debugger that allows
Mitrion-C applications to be tested and evaluated without the need to run them
in actual FPGA hardware
• A processor configurator, which adapts a
Mitrion Virtual Processor to the compiled Mitrion-C code.
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